The inference IP · RTL · In-memory computing
Xengra
the in-memory RTL IP
A Digital In-Memory Computing neural accelerator that keeps weights resident in the SRAM array and computes in place, cutting the weight-movement energy that dominates conventional NPUs. FPGA-proven today, on a path to ASIC.
Compute where the data already lives
Conventional accelerators burn most of their energy moving weights between memory and compute. Ximplic Xengra keeps weights pinned inside the SRAM array and does the multiply-accumulate in place. On always-on models, weight movement stops being the dominant cost.
A tiled, weight-stationary in-memory engine. Each cluster holds a MAC array; the post-processing (scaling, activation, requantization, residual add, pooling) sits outside the compute macro so the datapath stays flexible across edge models. Precision is configurable at runtime from INT8 down to INT1.
The compute-macro interface is frozen between the FPGA prototype and the ASIC. Ximplic Xengra runs today on an FPGA, with block RAM standing in for the array, and migrates to a custom low-voltage SRAM macro at silicon, with no change to the surrounding logic. De-risk on hardware now and carry the validated design into the end product.
The datapath, per cluster
- — Input buffer + sparsity engine
- — DIMC macro: MAC in memory
- — Pipelined adder tree
- — Post-process: scale · LUT · requant
- — Eltwise add · pooling · on-chip memory
Efficiency from several techniques combined
In-memory MAC array
Weights pinned in the SRAM array; activations stream in, no weight movement.
Multi-precision, runtime
INT8 to INT1, configurable per layer for more throughput, less energy.
Dual sparsity engine
Input and weight sparsity skip needless work for measured energy savings.
Flexible post-processing
A 256-entry LUT approximates any activation, plus inline residual add and pooling.
Standard SoC interfaces
AMBA AXI4 and AXI4-Lite, memory-mapped control, plus AXI4 DMA from DRAM.
FPGA-to-ASIC contract
Frozen compute-macro interface: validate on FPGA, migrate to ASIC without logic rework.
Spiking networks, too
Runs rate-coded spiking neural networks (integrate-and-fire / LIF) in a single pass, board-validated, on the same array as CNNs and transformers.
Two ways it integrates into the SoC
From a low-risk drop-in to an in-place memory upgrade. Option A is available and FPGA-tested today. Option B is on the way.
External Accelerator
- — Sits next to the host SoC as separate IP
- — Standard AXI bus connection
- — Zero changes to host silicon
In-Place Memory Upgrade
- — Replaces passive on-chip SRAM
- — Same footprint, memory now computes
- — Zero data movement
Technical summary
- Architecture
- Weight-stationary digital in-memory MAC
- Post-processing
- LUT activation · requant · eltwise · pool
- Compute array
- Configurable, multi-cluster
- Host interface
- AXI4-Lite control + AXI4 DMA
- Precision
- INT8 / INT4 / INT2 / INT1, runtime
- FPGA prototype
- Proven end to end on FPGA
- Sparsity
- Input + weight, row/column masking
- Model classes
- CNN · transformer-class · rate-coded SNN
- ASIC target
- Custom low-voltage SRAM macro
- Toolchain
- Vextyl + Vyzora
Built for always-on edge inference
It wins where models are small and run continuously, the workloads that drain a battery on a conventional NPU.
Keyword spotting
Wake-word and command detection at sub-mW duty cycles.
Anomaly detection
Predictive-maintenance autoencoders on industrial sensor streams.
Compact CNN inference
MobileNet-class person, gesture and presence sensing.
Sensor-hub AI
Low-power classification in always-on sensor hubs.
A validated Xengra IP package
- Xengra RTLSynthesisable DIMC core with configurable, multi-cluster array.
- SoC integration wrapperAXI4-Lite control, AXI4 DMA, and a command/interrupt model for the host SoC.
- FPGA prototype flowPackaging, block-design and bitstream flow proven on FPGA.
- Verification suiteSelf-checking testbenches with golden-value and board-correlation checks.
- VextylThe Compiler: ONNX-to-hardware toolchain that deploys any model onto Core.
- VyzoraThe Virtual Prototype: SystemC model for early architecture and software work.
- DocsDesign spec, ASIC migration contract, and integration guidance.
From evaluation to integration
Scope
Share workloads and power budget; we confirm fit and array sizing.
Evaluate
Measure latency and energy on target workloads via the Virtual Prototype and FPGA.
Integrate
Wires into the SoC over AXI and deploys models with the compiler.
Tape out
Carry the frozen-interface Ximplic Xengra design into the target ASIC.
Proven on FPGA
Ximplic Xengra runs real models end-to-end on an FPGA, bit-exact against simulation.
| What | Status | Where |
|---|---|---|
| End-to-end inference, INT8 | Measured | FPGA, matches simulation |
| Multi-precision (INT4) deployment | Measured | FPGA, mixed precision |
| Three model families, one bitstream | Measured | Keyword spotting + anomaly detection + spiking NN |
| Keyword spotting (DS-CNN-L) | Measured | FPGA |
| Anomaly detection (MLPerf Tiny AD) | Measured | FPGA |
| Spiking NN (conv-SNN) | Measured | FPGA |
What's measured, stated plainly. Functional correctness and per-layer timing are measured on the FPGA prototype, where block RAM stands in for the in-memory array. Final power and efficiency depend on the custom SRAM macro and process node at ASIC. We share the methodology and the FPGA results under NDA.
Frequently asked
What does integrating Ximplic Xengra into an SoC involve?
The core wires in like any standard peripheral IP: an AXI4-Lite interface for memory-mapped control and AXI4 DMA from system memory, with a command and interrupt model for the host. The package includes an SoC integration wrapper and integration guidance, and Ximplic Vyzora lets the team validate the driver path in software before hardware.
Is the RTL portable across process nodes and foundries?
The datapath is fully digital and synthesisable: no analog compute, no exotic devices. On FPGA, block RAM stands in for the array; at ASIC, a custom low-voltage SRAM macro takes its place behind a frozen compute-macro interface, so the surrounding logic carries across without rework.
What verification collateral is included?
Self-checking testbenches with golden-value checks and board-correlation checks against the FPGA prototype, plus the full FPGA prototype flow: packaging, block design and bitstream. Documentation covers the design spec, the ASIC migration contract and integration guidance.
What area, frequency and efficiency figures should we expect?
We state plainly what is measured: functional correctness and per-layer timing on the FPGA prototype, where block RAM stands in for the in-memory array. Final power, area and efficiency depend on the custom SRAM macro and the process node, so ASIC figures are design targets, not measurements. We share the methodology and the FPGA results under NDA.
What is the path from FPGA proof to our silicon?
The compute-macro interface is frozen between the FPGA prototype and the ASIC: validate the design on hardware now, then migrate the array to the custom low-voltage SRAM macro with no change to the surrounding logic. The engagement runs scope, evaluate, integrate over AXI, then tape-out, carrying the same validated design into the target ASIC. The IP is FPGA-proven today; it has not yet been taped out to silicon.
Designing an always-on AI SoC?
Building an always-on AI SoC that has to hit a tight power budget? Ximplic Xengra is the inference core that makes it work. Let's set up an evaluation tailored to the target workloads.