Energy-efficient AI for everyday devices
Always-on devices like wearables, cameras and sensors burn most of their power just moving data to run AI. We design and license the inference block that removes that cost, so AI runs all day on a battery. Proven in software and on FPGA today.
What drains the battery is moving data, not the math
An AI model is millions of numbers, called weights. On a normal chip, every prediction sends those numbers back and forth between the memory that holds them and the part that does the math. On a device that's running AI all the time, it's that constant movement that drains the battery, not the math itself.
Energy one AI prediction burns. The math is the actual computation; everything else is energy wasted moving weights between memory and compute. Longer bar means more total energy.
Same model, a fraction of the power. The energy that used to move data now does the math.
Illustrative split, not measured values. Per-workload figures come from Ximplic Vyzora.
So we do the math inside the memory
Instead of carrying the weights over to a separate compute block, the chip does the math right where they already sit, inside the memory. Almost nothing moves, so the same model runs on a small fraction of the power. For any device that has to run AI on a battery, this is the part that makes it possible, and the whole path can be checked before any commitment:
Evaluate
VyzoraRun any AI model on a virtual copy of the chip and measure power up front. Software only, no hardware.
Map
VextylThe compiler maps any trained ONNX model onto the memory array, quantized and checked against the hardware.
Integrate
XengraThe synthesisable RTL drops into your SoC over a standard AMBA AXI bus, like any other IP block.
Silicon
SilvenA hardened, drop-in macro. On the roadmap.
On the roadmapIP, generated by a proprietary flow
What we license is the inference IP. What makes it different is how it's made: instead of hand-building each block, a proprietary design flow maps any trained model onto the hardware and proves it automatically. Because it's a flow, not a one-off design, it re-targets new compute technologies fast.
- The productInference IP blocks you license into your SoC, the output of the flow.
- The differenceA proprietary flow generates and proves each block automatically: weeks, not years.
- AdaptableThe same flow re-targets new compute technologies as they arrive.
Built as a flow, it re-targets new compute technologies.
Carrying new ways of computing from research to real silicon.
Computing is hitting an energy wall. The largest gains no longer come from faster transistors, but from new ways of computing, like doing the work inside memory. The hard part has never been the idea. It is turning it into hardware that actually works.
Compute-in-memory is where we start, because that is where the energy savings are clearest. But the flow we are building isn't tied to one technology: mapping a model onto an unconventional array and proving it correct is a pattern that repeats every time a new kind of compute leaves the lab.
Built around that pattern, it is meant to carry each breakthrough from research to real silicon, so better ways of computing reach everyday devices in years, not decades.
Bring Ximplic into your chip
Tell us a bit about your workloads and platform, and we'll set up an evaluation under NDA, then talk through licensing the IP into your design. Happy to discuss a partnership or a role too.
Email info@ximplic.com · Groningen, The Netherlands