The flow · Virtual prototype

Vyzora
the Virtual Prototype

A cycle-approximate, SystemC TLM-2.0 model of the XIM Digital In-Memory Computing accelerator IP. Benchmark workloads, explore power and performance, and design the accelerator into a target SoC, months before RTL or silicon and at zero EDA cost.

How it works

SystemC TLM-2.0 native ARM AMBA AXI4 / AXI4-Lite IP-XACT register map

SoC integrationAXI4 · drop-in IP

INT8–INT1PRECISION

TLM-2.0SYSTEMC

R²=1.00vs RTL (dense)

Design around the accelerator before the silicon exists

An executable, cycle-approximate model of the accelerator IP. Drops into a SystemC platform to run any workload, returning trustworthy cycles, latency and energy to drive architecture and software decisions.

The accelerator keeps weights resident in the SRAM array and computes in place. It targets the workloads that run continuously on battery: keyword spotting, anomaly detection, sensor fusion and compact vision.

De-risk the integration today. Measures latency and energy on any model, validates the driver path, and explores operating points, all in software with no hardware and no proprietary EDA.

Probe the accelerator from any testbench

A stable C++ probe API exposes the numbers that matter, per inference:

// link libxim_component.a into your SoC VP auto xim = new xim_accelerator_tlm("xim", /*clusters*/4); xim->set_operating_point(0.6, 250.0); // V, MHz // ...run your command stream over AXI... xim->get_cycle_count(); // wall-clock cycles xim->get_compute_latency_ns(); // latency xim->get_energy_pJ(); // dynamic + leakage xim->get_compute_tops_per_watt();

Everything needed to evaluate and integrate

Configurable compute array

INT8 / INT4 / INT2 / INT1, sized to a target power and area budget.

RTL-correlated timing

R² = 1.0000 vs RTL on the dense path, FPGA-calibrated to ±5% per layer.

Standard SoC interfaces

ARM AMBA AXI4 + AXI4-Lite with an IEEE 1685-2014 IP-XACT register map.

Energy & DVFS modeling

Dynamic and leakage energy with DVFS sweeps for TOPS/W and battery life.

Drop-in integration

Shim template, RISC-V reference SoC and 8 hooks. Integrate in days.

Target workloads, measured

20+ MAC-honest model builders with HTML/CSV reports and comparison.

Technical summary

Model type: Cycle-approximate SystemC TLM-2.0
Scaling: Configurable, parallel
Host interface: AXI4-Lite control + AXI4 DMA
Integrator API: 8 callback hooks + probe getters
Compute array: Configurable, in-memory
Precision: INT8 / INT4 / INT2 / INT1
Register map: IEEE 1685-2014 IP-XACT XML
Timing profiles: FPGA + ASIC design-intent
Toolchain: Open SystemC, no proprietary EDA
Validation: RTL co-sim + FPGA calibration

Built for always-on edge inference

In-memory computing wins when models are small and run all the time, exactly the workloads that flatten a battery on a conventional NPU.

Audio

Keyword spotting

Always-listening wake-word detection (DS-CNN) at sub-mW duty cycles.

Sensors

Anomaly detection

Predictive-maintenance autoencoders on IoT sensor streams, on-device.

Vision

Compact CNN inference

MobileNet-class person, gesture and presence sensing for wearables.

Fusion

Sensor-hub AI

Low-power fusion in always-on hubs with weights resident on-chip.

A complete integration kit

The accelerator coreSystemC IP-block model plus a static library to link in.
AMBA reference wrappersAXI4 wrappers verified against the ARM AMBA TLM-2.0 kit.
Integration shim & reference SoCDrop-in template plus a RISC-V reference platform.
Workload runner & benchmarks20+ model builders with HTML/CSV performance reports.
IP-XACT register descriptionIEEE 1685-2014 XML, one source for driver and docs.
Calibration & test suitesRTL co-sim, AXI-compliance and golden-value regression tests.
Integration guide & onboardingStep-by-step docs, AXI protocol BVI and model description.

From evaluation to design-in

Scope

Share target workloads, power budget and platform. We confirm fit.

Evaluate

Run customer models under NDA, measuring latency and energy.

Integrate

Plug into a SystemC platform via the shim and AXI sockets.

Design-in

Move the XIM IP into RTL with a validated path.

Numbers worth trusting

Validated against RTL co-simulation and FPGA measurement.

Configuration	Precision	Vyzora cycles	RTL cycles	Δ
256×256 dense	INT8	2,574	2,573	+0.0%
256×256 dense	INT4	1,542	1,545	−0.2%
128×128 dense	INT8	1,294	1,293	+0.1%
64×64 · 50% sparse	INT8	398	397	+0.3%

Modeling transparency. Ximplic Vyzora is FPGA-calibrated end-to-end for the DS-CNN-L reference workload. Other models (MobileNet, ResNet, transformers, LLMs) are MAC-honest analytic projections for relative comparison and architecture exploration, and reports label them as estimates. We share the full calibration methodology and validity envelope under NDA so teams can judge fit for their own use case.

Frequently asked

What can we measure with Ximplic Vyzora?

Per-inference cycle counts, compute latency, dynamic plus leakage energy, and TOPS/W, exposed through a stable C++ probe API. Operating-point sweeps across voltage and frequency let you explore DVFS trade-offs and estimate battery life for a target workload.

How does cycle-approximate accuracy relate to the RTL?

The model is correlated to RTL co-simulation, with R² = 1.0000 on the dense path and dense configurations matching RTL cycle counts within a fraction of a percent, and it is FPGA-calibrated to ±5% per layer. The DS-CNN-L reference workload is calibrated end to end; other models are MAC-honest analytic projections, and reports label them as estimates.

What do we need to start an evaluation?

Target workloads, a power budget and a description of the platform; we confirm fit first. Customer models run under NDA, and we share the calibration methodology and validity envelope the same way. No hardware and no proprietary EDA are needed; everything runs on open SystemC on standard machines.

How does it plug into an existing SoC simulation?

Ximplic Vyzora is native SystemC TLM-2.0: link the static library, connect over the AXI4 and AXI4-Lite wrappers verified against the ARM AMBA TLM-2.0 kit, and drive it from your platform or testbench. An integration shim template and eight callback hooks handle the glue, and a RISC-V reference SoC is included if you don't have a platform yet. Typical integration takes days.

Do the results carry over to the RTL?

That is the point of the flow. Ximplic Vextyl targets both the virtual prototype and the RTL, so the model measured in software is the same deployment that runs on Ximplic Xengra, with timing validated against RTL co-simulation and FPGA measurement. The IP is FPGA-proven today; silicon is on the roadmap.

Partner with Ximplic

Plug the XIM accelerator into a target design

Scoping an always-on AI SoC, benchmarking for a product roadmap, or ready to design-in? Let's set up an evaluation of Ximplic Vyzora, tailored to target workloads.

Email info@ximplic.com · ximplic.com

Vyzorathe Virtual Prototype