ASIC/RTL Design Intern
Internship · Hardware · Groningen, The Netherlands
Our proprietary flow generates compute-in-memory hardware from RTL to GDS, and the next step is silicon. You carry one of our designs through the physical-design backend toward a fabrication shuttle, with direct guidance from the founders.
What you'll do
- Set up our physical build flow on the target PDK and reproduce the current baseline; harden a small trial block end to end as a dry run
- Harden our compute-in-memory macro to DRC/LVS-clean signoff: antenna, density, fill, guard ring, and SRAM-macro integration
- Run multi-corner static timing analysis and close timing on the block
- Integrate the macro into the shuttle's top-level chip harness and close top-level DRC, LVS, and timing, including the host-controller connection
- Prepare and submit the final GDS for the fabrication shuttle, passing the full tape-out checklist
- Prepare silicon bring-up: a test-board outline and a validation checklist for the returned chips
What we look for
- MSc student in electrical engineering, microelectronics, or a related field
- Coursework or project experience with digital design flows: synthesis, place-and-route, or timing analysis
- Working knowledge of Linux, with some scripting in Python or Tcl
- Systematic debugging habits and clear reporting in English
- Preferably already studying at a university in the Netherlands; we cannot sponsor visas at this stage
Nice to have
- Hands-on time with OpenROAD/OpenLane or a commercial backend tool (Innovus, ICC2, Fusion Compiler)
- PDK exposure (e.g. sky130)
- RTL experience (Verilog or SystemVerilog)
- SRAM or hard-macro integration experience
- PCB or board-level experience
What you get
- Work on a real design headed for fabrication
- Direct mentorship from the founding team
- An end-to-end view of an RTL-to-GDS flow
Ximplic is an equal opportunity employer. We welcome applications from people of all backgrounds and select on ability and motivation alone.